The global race toward next-generation high-bandwidth memory is intensifying as SK hynix expands both manufacturing and advanced packaging capacity to support HBM4. The rapid build-out of AI infrastructure is tightening supply across the wider memory market, pushing up prices for conventional DRAM products such as DDR5 and forcing OEMs to reassess system build plans for 2026 and 2027.

Industry pressure is no longer limited to wafer output alone. Packaging and test throughput has emerged as a critical bottleneck, particularly for HBM products where multiple DRAM layers are stacked into a single high-value package. According to industry reporting, memory makers are struggling to increase output fast enough to meet demand from data centre GPUs and AI accelerators.

Against this backdrop, SK hynix has announced plans to invest approximately 19 trillion won in a new advanced packaging and test facility, known as P&T7, at Cheongju Technopolis in South Korea. Construction is expected to begin in April, with completion targeted for the end of 2027. The facility is designed to support volume production of HBM modules, where yield losses can be particularly costly due to the complexity and value of stacked assemblies.

At the roadmap level, the memory industry is transitioning from HBM3E to HBM4. In a January update, TrendForce said SK hynix expects HBM3E to remain the dominant product throughout 2026, potentially accounting for around two-thirds of total HBM shipments, while HBM4 ramps. The same analysis highlights SK hynix’s advanced packaging partnership with TSMC and the role of the Cheongju M15X fab in supporting both HBM3E and HBM4 output.

Capacity timing has become central to procurement planning across the electronics supply chain. Reports from South Korea indicate that SK hynix expects to complete the first clean room at its M15X fab in May next year and begin pilot operations shortly afterwards. If schedules hold, volume output from the first clean room could begin around November. The company is also planning to introduce 10nm-class “1c” DRAM lines to support future HBM generations, signalling a capacity ramp that extends well beyond 2027.

At CES 2026, supplier messaging around HBM4 focused on readiness for next-generation AI accelerators. HBM4 has been described as the most significant architectural overhaul of the technology to date. SK hynix unveiled a 16-layer HBM4 device offering 48GB capacity and bandwidth exceeding 2TB/s, with mass production targeted for the third quarter of 2026. Industry reports indicate that samples are already being delivered to customers such as Nvidia for upcoming AI platforms.

This aggressive prioritisation of HBM is already visible in downstream pricing. DDR5 memory kits that sold for under US$100 a year ago are now priced well above US$300, reflecting tight DRAM and NAND supply. As suppliers continue to prioritise HBM output and advanced packaging capacity, availability of mainstream DRAM is expected to remain uneven.

Looking ahead, key milestones to watch include progress on the M15X clean-room build-out, early HBM4 yield and qualification results, and how quickly new packaging capacity such as P&T7 can be translated into shippable HBM modules. Together, these developments highlight how advanced packaging has become a decisive innovation frontier in the global memory industry.