Taiwan’s National Institutes of Applied Research has introduced a substrate-less chip-level packaging platform designed to enhance system integration, reduce costs and support next-generation AI-driven semiconductor applications.

Taiwan Unveils Substrate-Less Chip-Level Packaging to Boost Advanced Semiconductor Innovation

Taiwan’s National Institutes of Applied Research (NIAR) has unveiled a new open research and development platform featuring a substrate-less chip-level packaging technique, marking a significant step forward in the country’s advanced semiconductor packaging ecosystem. The announcement was made by NIAR’s Taiwan Semiconductor Research Institute (TSRI) at a press event in Taipei.

The newly introduced approach aims to shift Taiwan’s competitive advantage in the global semiconductor industry from traditional manufacturing excellence toward system integration and application-driven innovation. According to NIAR, advanced packaging will play a decisive role in enabling future artificial intelligence applications that demand higher performance, increased integration density and lower power consumption.

The platform is based on a proprietary Chip-on-Chip-on-Board (CoCoB) architecture, which differs from established technologies such as Chip-on-Wafer-on-Substrate (CoWoS), currently used in high-end applications by major foundries. While CoWoS enables dense integration of computing chips and high-bandwidth memory through interposers and substrates, the substrate layer introduces higher costs, longer signal paths and increased process complexity.

In contrast, the CoCoB architecture directly connects the interposer chip to the circuit board, eliminating the substrate entirely. This design significantly shortens signal transmission distances, enhances integration density and improves overall system performance. TSRI explained that one of the core technical challenges was ensuring reliable connectivity across thousands of micro-solder points, a problem addressed through the use of a flowable interface material beneath each solder ball.

By removing substrate-related costs and simplifying the manufacturing process, the new packaging technique is particularly attractive for academic institutions, research laboratories and startups seeking flexible, lower-cost platforms for heterogeneous integration experiments. NIAR emphasized that the open R&D model is intended to accelerate collaboration and broaden participation across the semiconductor research community.

To date, the initiative has attracted 16 professor-led research teams from Taiwan and international institutions, highlighting growing global interest in next-generation packaging solutions. The project underscores Taiwan’s strategic focus on advanced packaging as a foundation for future breakthroughs in AI, high-performance computing and system-level semiconductor innovation.


More Info(National Institutes of Applied Research (NIAR))

Keywords

advanced packaging , semiconductor innovation , chip-level packaging , AI chips , Taiwan semiconductors , system integration , heterogeneous integration , TSRI , NIAR

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